1. Technical Field
The present invention relates to a chip package including at least one stackable chip.
2. Background
Chip stacking technology can bring two chips close together, thereby enabling faster data transmission between the two chips and consuming less power. Memory chips can be stacked together to obtain a memory module with a large storage capacity. In addition to stacking two of the same chip, two chips with different functions may also be stacked together to combine different functions.
In a memory chip stack, each memory chip has a chip select (CS) terminal, which is used to enable the memory chip. For example, a DRAM chip can have a row address strobe (RAS), column address strobe, or chip select pin as a chip select terminal. When a signal is applied to the chip select terminal of a chip in a memory chip stack, the chip can be accessed, while other chips cannot.
Conventionally, signals applied to the chip select terminals of the memory chip stack flow through wires. Such wires need additional processes to form, which increases the manufacturing cost. Moreover, long wires cause signal delays by occupying more space, and results in a large chip package.